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Preliminary 2
Typical Applications * 3V Dual-Band GSM Handsets * Commercial and Consumer Systems * Portable Battery-Powered Equipment
RF3110
TRIPLE-BAND GSM/DCS/PCS POWER AMP MODULE
* GSM, E-GSM and DCS/PCS Products * GPRS Class 10 Compatible
2
POWER AMPLIFIERS
Pin 1 8.747 5.925 4.075 1.245 0.306
Product Description
The RF3110 is a high-power, high-efficiency power amplifier module with integrated power control. The device is self-contained with 50 input and output terminals. The power control function is also incorporated, eliminating the need for directional couplers, detector diodes, power control ASICs and other power control circuitry; this allows the module to be driven directly from the DAC output. The device is designed for use as the final RF amplifier in GSM/DCS and PCS handheld digital cellular equipment and other applications in the 880MHz to 915MHz, 1710MHz to 1785MHz and 1850MHz to 1910MHz bands. On-board power control provides over 35dB of control range with an analog voltage input; and, power down with a logic "low" for standby operation. Optimum Technology Matching(R) Applied
Si BJT Si Bi-CMOS
0.400 TYP 1.200 TYP 1.800 TYP 2.600 TYP 3.200 TYP 4.000 TYP 4.600 TYP 5.400 TYP 6.000 TYP 6.800 TYP 7.400 TYP 8.200 TYP 8.275 TYP 8.800 TYP 9.600 TYP 1.70 1.45 Pin 1 9.600 TYP 8.800 TYP 8.200 TYP 7.400 TYP 6.800 TYP 6.000 TYP 5.400 TYP 4.600 TYP 4.000 TYP 3.200 TYP 2.600 TYP 1.800 TYP 1.200 TYP 0.400 TYP 0.000 0.450 0.075 8.205 8.280 9.098 TYP 0.000 1.797 10.00 0.10 10.00 0.10
u
Package Style: Module
GaAs HBT SiGe HBT
VCC2
GaAs MESFET Si CMOS
Features * Complete Power Control Solution * Single 2.9V to 5.5V Supply Voltage
12 DCS IN 1 BAND SELECT 2 TX ENABLE 3 VBATT 4 VREG 5 VRAMP 6 GSM IN 7 8 VCC2 9 GSM OUT 10 VCC OUT 11 DCS OUT
* +35dBm GSM Output Power at 3.5V * +33dBm DCS/PCS Output Power at 3.5V * 55% GSM and 55% DCS/PCS EFF * 10mmx10mm Package Size
Ordering Information
RF3110 RF3110 PCBA Triple-Band GSM/DCS/PCS Power Amp Module Fully Assembled Evaluation Board
Functional Block Diagram
RF Micro Devices, Inc. 7628 Thorndike Road Greensboro, NC 27409, USA
Tel (336) 664 1233 Fax (336) 664 0454 http://www.rfmd.com
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RF3110
Absolute Maximum Ratings Parameter
Supply Voltage Power Control Voltage (VRAMP) Input RF Power Duty Cycle at Max Power Output Load VSWR Operating Case Temperature Storage Temperature
Preliminary
Rating
-0.5 to +6.0 -0.5 to +1.8 +11.5 37.5 8:1 -40 to +85 -55 to +150
Unit
VDC V dBm % C C Caution! ESD sensitive device.
RF Micro Devices believes the furnished information is correct and accurate at the time of this printing. However, RF Micro Devices reserves the right to make changes to its products without notice. RF Micro Devices does not assume responsibility for the use of the described product(s).
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POWER AMPLIFIERS
Parameter
Specification Min. Typ. Max.
Unit
Condition
Temp=+25 C, VCC =3.5V, VRAMP Max, VRAMP =VRAMP Max, PIN =6dBm, Freq=880MHz to 915MHz, 12.5% Duty Cycle, Pulse Width=577s
Overall (GSM Mode)
Operating Frequency Range Maximum Output Power 880 to 915 35.0 MHz dBm dBm 55 +6 -86 -88 Forward Isolation Second Harmonic Third Harmonic All other Non-Harmonic Spurious Input Impedance Input VSWR Output Load VSWR Output Load Impedance -35 -15 -30 50 2.5:1 8:1 50 1.6 0.25 V V dB pF A S -30 -5 -15 -36 % dBm dBm dBm dBm dBm dBm dBm
+34.5 +32.0
Total Efficiency Input Power Range Output Noise Power
+4
+8
Temp = 25C, VCC =3.5V, VRAMP =VRAMP Max Temp=+85 C, VCC =2.9V, VRAMP =VRAMP Max At POUT,MAX, VCC =3.5V Full output power guaranteed at minimum drive level RBW=100kHz, 925MHz to 935MHz, POUT > +5dBm RBW=100kHz, 935MHz to 960MHz, POUT > +5dBm TX_ENABLE=0V, PIN=+8dBm
POUT,MAX-5dBPower Control VRAMP
Power Control "ON" Power Control "OFF" Power Control Range VRAMP Input Capacitance VRAMP Input Current Turn On/Off Time Note: VRAMP Max=3/8*VBATT+0.18<1.6V 0.2 35 15
10 4
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Preliminary
Parameter
Overall Power Supply
Power Supply Voltage 2.9 Power Supply Current 2 1 2.7 2.8 7 10 3.5 5.5 10 2.9 V V A A V mA A
RF3110
Specification Min. Typ. Max. Unit Condition
Specifications Nominal operating limits, POUT <+33dBm DC Current at POUT,MAX PIN <-30dBm, VRAMP =0V, Temp=-40C to +85C TX Enable=High TX Enable=Low Temp=25C, VCC =3.5V, VRAMP =VRAMP Max, PIN =6dBm, Freq=1710MHz to 1785MHz, 12.5% Duty Cycle, pulse width=577s Temp=25C, VCC =3.5V, VRAMP =VRAMP Max, 1710MHz to 1785MHz 1850-1910MHz Temp=+85C, VCC =2.9V, VRAMP = VRAMP Max, 1710MHz to 1785MHz 1850MHz to 1910MHz At POUT,MAX, VCC =3.5V, 1710-1785MHz 1850-1910MHz Full output power guaranteed at minimum drive level RBW =100kHz, 1805MHz to 1880MHz and 1930MHz to 1990MHz, POUT > 34.5dBm, VCC =3.5V TX_ENABLE=0V, PIN =+8dBm POUT, = +32.5dBm
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POWER AMPLIFIERS
VREG Voltage VREG Current
Overall (DSC/PCS Mode)
Operating Frequency Range Maximum Output Power 1710 to 1910 +33 31.5 30 29.5 52 45 +6 MHz dBm dBm dBm dBm % +8 -77 dBm dBm
+32
Total Efficiency Input Power Range Output Noise Power
45 +4
Forward Isolation Second Harmonic Third Harmonic All other Non-Harmonic Spurious Input Impedance Input VSWR Output Load VSWR Output Load Impedance
-37 -25 -30 50 8:1 50
-30 -15 -15 -36 2.5
dBm dBm dBm dBm
1.6 0.25 V V dB pF A A s
P+5dBPower Control VRAMP
Power Control "ON" Power Control "OFF" Power Control Range VRAMP Input Capacitance VRAMP Input Current Turn On/Off TIme Note: VRAMP max=3/8*VBATT+0.18<1.6V 0.2 33 15
10 10 4
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RF3110
Parameter
Overall Power Supply
Power Supply Voltage 2.9 Power Supply Current 3.5 5.5 1.3 1 2.7 2.8 7 10 10 2.9 V V A A V mA A
Preliminary
Specification Min. Typ. Max. Unit Condition
Specifications Nominal operating limits, POUT <+33dBm DC Current at POUT,MAX PIN <-30dBm, VRAMP =0V, Temp=-40C to +85C TX Enable=High TX Enable=Low
2
POWER AMPLIFIERS VREG Voltage VREG Current
2-264
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Preliminary
Pin 1 2 3 4 5 6 Function DCS IN BAND SELECT TX ENABLE VBATT VREG VRAMP Description
RF input to the DCS band. This is a 50 input. Allows external control to select the GSM or DCS band with a logic high or low. A logic low enables the GSM band whereas a logic high enables the DCS band. This signal enables the PA module for operation with a logic high. Once TX Enable is asserted the RF output level will increase to 0dBm. Power supply for the module. This should be connected to the battery. Regulated voltage input for power control function. (2.8V nom) Ramping signal from DAC. A simple RC filter may need to be connected between the DAC output and the VRAMP input depending on the baseband selected. The ramping profiles shown later in the data sheet are recommended profiles for meeting the GSM specification for burst timing and transient spectrum. RF input to the GSM band. This is a 50 input. Controlled voltage input to driver stage for GSM bands. This voltage is part of the power control function for the module. This node must be connected to VCC out. RF output for the GSM band. This is a 50 output. The output load line matching is contained internal to the package. Controlled voltage output to feed VCC2. This voltage is part of the power control function for the module. It can not be connected to anything other than VCC2, nor can any component be placed on this node (i.e. decoupling capacitor). RF output for the DCS band. This is a 50 output. The output load line matching is contained internal to the package. Controlled voltage input to DCS driver stage. This voltage is part of the power control function for the module. This node must be connected to VCC out
RF3110
Interface Schematic
2
POWER AMPLIFIERS
7 8 9 10
GSM IN VCC2 GSM OUT VCC OUT
11 12 Pkg Base
DCS OUT VCC2 GND
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RF3110
Pin Out
VCC2 PIN #1
Preliminary
DCS IN
PCS OUT
2
POWER AMPLIFIERS
BAND SELECT
TX EN
VBATT
VCC
10.0000
VREG
VRAMP
GSM IN VCC2
GSM OUT
10.0000
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Preliminary
Application Schematic
50 strip DCS/PCS IN 180 1 BAND SELECT TX ENABLE VBATT VREG 15 k** VRAMP GSM IN 180 50 strip 6 7 8 9 50 strip 2 3 4 5 10 12 11 50 strip
RF3110
DCS/PCS OUT
2
POWER AMPLIFIERS
GSM OUT
** Used to filter noise and spurious from base band.
Evaluation Board Schematic
(Download Bill of Materials from www.rfmd.com.)
P1 1 GND CON1 50 strip DCS/PCS IN 180 1 BAND SELECT TX ENABLE VBATT 3.3 F* 15 k** 2 3 4 VREG 5 6 7 8 180 9 50 strip GSM OUT 10 12 11 50 strip DCS/PCS OUT P2-1 P2 1 VCC CON1
VRAMP GSM IN
1 nF* 50 strip
*Not required in most applications ** Used to filter noise and spurious from base band.
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Preliminary
Theory of Operation
Overview The RF3110 is a triple-band GSM/DCS/PCS power amplifier module that incorporates an indirect closed loop method of power control. This simplifies the phone design by eliminating the need for the complicated control loop design. The indirect closed loop is fully self contained and required does not require loop optimization. It can be driven directly from the DAC output in the baseband circuit. Theory of Operation The indirect closed loop is essentially a closed loop method of power control that is invisible to the user. Most power control systems in GSM sense either forward power or collector/drain current. The RF3110 does not use a power detector. A high-speed control loop is incorporated to regulate the collector voltages of the amplifier while the stages are held at a constant bias. The VRAMP signal is multiplied and the collector voltages are regulated to the multiplied VRAMP voltage. The basic circuit is shown in the following diagram.
VBATT TX ENABLE VRAMP
RF3110
There are several key factors to consider in the implementation of a transmitter solution for a mobile phone. Some of them are: * * * * * * * * * * * Effective efficiency (eff) Current draw and system efficiency Power variation due to Supply Voltage Power variation due to frequency Power variation due to temperature Input impedance variation Noise power Loop stability Loop bandwidth variations across power levels Burst timing and transient spectrum trade offs Harmonics
2
POWER AMPLIFIERS
H(s)
RF IN TX ENABLE
RF OUT
Talk time and power management are key concerns in transmitter design since the power amplifier has the highest current draw in a mobile terminal. Considering only the power amplifier's efficiency does not provide a true picture for the total system efficiency. It is important to consider effective efficiency which is represented by EFF. (EFF considers the loss between the PA and antenna and is a more accurate measurement to determine how much current will be drawn in the application). EFF is defined by the following relationship (Equation 2):
m
By regulating the power, the stages are held in saturation across all power levels. As the required output power is decreased from full power down to 0dBm, the collector voltage is also decreased. This regulation of output power is demonstrated in Equation 1 where the relationship between collector voltage and output power is shown. Although load impedance affects output power, supply fluctuations are the dominate mode of power variations. With the RF3110 regulating collector voltage, the dominant mode of power fluctuations is eliminated.
a P N - PIN
-------------------------------- 100 EFF = n = 1 P DC
(Eq. 4) Where Pn is the sum of all positive and negative RF power, PIN the input power and PDC is the delivered DC power. In dB the formula becomes (Equation 3):
P PA + P LOSS ----------------------------10 P IN ------10
P dBm
( 2 V CC - V SAT ) = 10 log -------------------------------------------3 8 R LOAD 10
2
10 - 10 EFF = -----------------------------------------------V BAT I BAT 10
(Eq. 3)
(Eq. 1)
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RF3110
Where PPA is the output power from the PA, PLOSS the insertion loss, PIN the input power to the PA and PDC the delivered DC power. The RF3110 improves the effective efficiency by minimizing the PLOSS term in the equation. A directional coupler may introduce 0.4dB to 0.5dB loss to the transit path. To demonstrate the improvement in effective efficiency consider the following example: Conventional PA Solution:
Preliminary
3 V RAMP -- V BATT + 0.18 8
(Eq. 4)
2
POWER AMPLIFIERS
Note: Output power is limited by battery voltage. The relationship in Equation 4 does not limit output power. Equation 4 limits the VRAMP voltage to correspond with the battery voltage. Due to reactive output matches, there are output power variations across frequency. There are a number of components that can make the effects greater or less. The components following the power amplifier often have insertion loss variation with respect to frequency. Usually, there is some length of microstrip that follows the power amplifier. There is also a frequency response found in directional couplers due to variation in the coupling factor over frequency, as well as the sensitivity of the detector diode. Since the RF3110 does not use a directional coupler with a diode detector, these variations do not occur. Input impedance variation is found in most GSM power amplifiers. This is due to a device phenomena where CBE and CCB (CGS and CSG for a FET) vary over the bias voltage. The same principle used to make varactors is present in the power amplifiers. The junction capacitance is a function of the bias across the junction. This produces input impedance variations as the Vapc voltage is swept. Although this could present a problem with frequency pulling the transmit VCO off frequency, most synthesizer designers use very wide loop bandwidths to quickly compensate for frequency variations due to the load variations presented to the VCO. The RF3110 presents a very constant load to the VCO. This is because all stages of the RF3110 are run at constant bias. As a result, there is constant reactance at the base emitter and base collector junction of the input stage to the power amplifier.
PPA = +33 dBm PIN = +6 dBm PLOSS = -0.4 dB VBAT = 3.5 V IBAT = 1.1 A
RF3110 Solution:
EFF = 47.2%
PPA = +33 dBm PIN = +6 dBm PLOSS = 0 dB VBAT = 3.5 V IBAT = 1.1 A
EFF = 51.72%
The RF3110 solution improves effective efficiency 5%. Output power does not vary due to supply voltage under normal operating conditions if VRAMP is sufficiently lower than VBATT. By regulating the collector voltage to the PA the voltage sensitivity is essentially eliminated. This covers most cases where the PA will be operated. However, as the battery discharges and approaches its lower power range the maximum output power from the PA will also drop slightly. In this case it is important to also decrease VRAMP to prevent the power control from inducing switching transients. These transients occur as a result of the control loop slowing down and not regulating power in accordance with VRAMP. The switching transients due to low battery conditions are regulated by incorporating the following relationship limiting the maximum VRAMP voltage (Equation 2). Although no compensation is required for typical battery conditions, the battery compensation required for extreme conditions is covered by the relationship in Equation 4. This should be added to the terminal software.
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Preliminary
Noise power in PA's where output power is controlled by changing the bias voltage is often a problem when backing off of output power. The reason is that the gain is changed in all stages and according to the noise formula (Equation 5),
RF3110
Harmonics are natural products of high efficiency power amplifier design. An ideal class "E" saturated power amplifier will produce a perfect square wave. Looking at the Fourier transform of a square wave reveals high harmonic content. Although this is common to all power amplifiers, there are other factors that contribute to conducted harmonic content as well. With most power control methods a peak power diode detector is used to rectify and sense forward power. Through the rectification process there is additional squaring of the waveform resulting in higher harmonics. The RF3110 address this by eliminating the need for the detector diode. Therefore the harmonics coming out of the PA should represent the maximum power of the harmonics throughout the transmit chain. This is based upon proper harmonic termination of the transmit port. The receive port termination on the T/R switch as well as the harmonic impedance from the switch itself will have an impact on harmonics. Should a problem arise, these terminations should be explored. The RF3110 incorporates many circuits that had previously been required external to the power amplifier. The shaded area of the diagram below illustrates those components and the following table itemizes a comparison between the RF3110 Bill of Materials and a conventional solution:
Component Conventional Solution $0.80 $0.20 $0.05 $0.05 $0.05 $0.12 $1.27 RF3110 N/A N/A N/A N/A N/A N/A $0.00
F2 - 1 F3 - 1 F TOT = F1 + --------------- + ------------------G1 G2 G1
(Eq. 5)
2
POWER AMPLIFIERS
the noise figure depends on noise factor and gain in all stages. Because the bias point of the RF3110 is kept constant the gain in the first stage is always high and the overall noise power is not increased when decreasing output power. Power control loop stability often presents many challenges to transmitter design. Designing a proper power control loop involves trade-offs affecting stability, transient spectrum and burst timing. In conventional architectures the PA gain (dB/ V) varies across different power levels, and as a result the loop bandwidth also varies. With some power amplifiers it is possible for the PA gain (control slope) to change from 100dB/V to as high as 1000dB/V. The challenge in this scenario is keeping the loop bandwidth wide enough to meet the burst mask at low slope regions which often causes instability at high slope regions. The RF3110 loop bandwidth is determined by internal bandwidth and the RF output load and does not change with respect to power levels. This makes it easier to maintain loop stability with a high bandwidth loop since the bias voltage and collector voltage do not vary. An often overlooked problem in PA control loops is that a delay not only decreases loop stability it also affects the burst timing when, for instance the input power from the VCO decreases (or increases) with respect to temperature or supply voltage. The burst timing then appears to shift to the right especially at low power levels. The RF3110 is insensitive to a change in input power and the burst timing is constant and requires no software compensation. Switching transients occur when the up and down ramp of the burst is not smooth enough or suddenly changes shape. If the control slope of a PA has an inflection point within the output power range or if the slope is simply to steep it is difficult to prevent switching transients. Controlling the output power by changing the collector voltage is as earlier described based on the physical relationship between voltage swing and output power. Furthermore all stages are kept constantly biased so inflection points are nonexistent. Rev A0 010921
Power Control ASIC Directional Coupler Buffer Attenuator Various Passives Mounting Yield (other than PA) Total
Note: Output power is limited by battery voltage. The relationship in Equation 4 does not limit output power. Equation 4 limits VRAMP to correspond with the battery voltage.
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RF3110
Preliminary
1 2 3
14 13 12 11 10 9 8
2
POWER AMPLIFIERS
4 5 6 7
From DAC
*Shaded area eliminated with Indirect Closed Loop using RF3110
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RF3110
Evaluation Board Layout Board Size 2.0" x 2.0"
Board Thickness 0.032", Board Material FR-4, Multi-layer
Preliminary
2
POWER AMPLIFIERS
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